1. Field of the Invention
The present invention relates to a basic cell design method that is used in the design stage of a semiconductor devices such as gate arrays and standard cells, a layout design method for designing the layout of a logic circuit in which basic cells are combined, a design device for executing these methods, and a program for causing a computer to execute these methods.
2. Description of the Related Art
In designing the layout of a logic circuit, a step of arranging logic gates in accordance with logic circuit information that includes information on the number of logic gates and the connection relations between these gates and a step of connecting the logic gates by wiring are carried out in succession. The logic gates that are included in a logic circuit may include a plurality of types. Methods of using circuit layout design devices for automatically determining the arrangement of logic gates have been disclosed (JP-A-2000-067094).
Explanation first regards one example of a layout design method in which the logic gates that are the basis of basic cells used in layout design are assumed to be inverters. FIG. 1 shows an example of the configuration of a basic cell.
A basic cell that is an inverter includes PMOS transistor 1 and NMOS transistor 2. Gate electrode 102 of PMOS transistor 1 and NMOS transistor 2 is connected to first-layer wiring 120 by way of contact hole 101. This first-layer wiring 120 is input wiring Tin.
The drain electrodes of PMOS transistor 1 and NMOS transistor 2 are connected to first-layer wiring 122 by way of contact holes 103. This first-layer wiring 122 is output wiring Tout.
Each of the source electrodes of PMOS transistor 1 and NMOS transistor 2 is connected to first-layer wiring 124 and 126 by way of contact holes 105 and 107, respectively. Although not shown in the figure, first-layer wiring 124 and 126 are each connected to the wiring of a second and subsequent layers by way of through-holes.
As shown in FIG. 1, the patterns that make up a basic cell are each arranged within cell area 150. The outermost periphery of each of the patterns is separated by a prescribed distance from the cell boundary of cell area 150 such that none of the patterns contacts the cell boundary. This configuration is adopted to prevent shorts between the outermost peripheries of patterns and the patterns of adjacent basic cells when a plurality of basic cells is arranged in proximity. Patterns are thus arranged within cell area 150 with a margin from the cell boundary.
Explanation next regards an example of a circuit when a plurality of inverters shown in FIG. 1 is connected. FIG. 2 shows an example of a circuit in which a plurality of inverters is connected. As shown in FIG. 2, inverters 141, 142, 143, and 144 are connected in a series. In addition, the output of inverter 143 is branched and connected to both the input of inverter 144 and the input of inverter 145.
A brief explanation is here presented regarding a design device for automatically arranging basic cells in accordance with the circuit shown in FIG. 2.
The design device is an information processor such as a CAD (Computer-Aided Design) tool. The design device includes: a memory unit for storing information such as the configuration of the above-described basic cell, the design tool, and layout rules; a control unit for carrying out operations for determining layout; an output unit for supplying the layout results as output; and a console unit by which a designer applies instructions as input. When the designer manipulates the console unit to enter logic circuit information and instructions indicating that layout is to be designed, the control unit reads information of the basic cell, design tool, and layout rules from the memory unit, arranges the basic cell in accordance with the logic circuit information, and supplies the layout results as output to the output unit.
Explanation next regards the layout results in which the above-described design device has been used to arrange basic cells in accordance with the circuit shown in FIG. 2. FIG. 3 shows an example of the layout when the basic cells as shown in FIG. 1 are used to realize the circuit shown in FIG. 2.
As shown in FIG. 3, basic cells of inverters 141-145 shown in FIG. 2 are arranged with cell boundaries in contact. First-layer wiring 128, which is the output wiring Tout of inverter 141, is connected to first-layer wiring 129 of input wiring Tin of inverter 142 by way of through-hole 110, second-layer wiring 130, and through-hole 111. The inter-cell connections of inverters 142, 143, 144, and 145 are similarly realized by second-layer wiring. Although the inter-cell connections are here realized by second-layer wiring, it is assumed that the inter-cell connections are realized by low-resistance wiring material of a second or subsequent layers and the connections are not necessarily limited to the second-layer wiring.
The layout rules here employed stipulate that inter-cell connections be realized by second-layer wiring and that cells be arranged such that the distance of the second-layer wiring that connects cells together be minimized.
However, the above-described layout method has several problems as described below.
The first problem is the high resistance of the connections between adjacent cells. This problem occurs because the connections between adjacent cells are realized by way of through-holes using the wiring material of second and subsequent layers, and the through-hole resistance, being greater than the wiring of second and subsequent layers, increases the resistance of inter-cell connections.
The second problem is the need for many wiring tracks of the second and subsequent layers and the consequent increase in chip size. This problem occurs because the wiring material of second and subsequent layers must be used in the connections between adjacent cells.